On-Site
Full-Time
Bengaluru, Karnataka
India
Skills
Verilog
RTL Design
RTL Coding
About the Role
RTL Design, CAD
Work Location: Bangalore
Full-Time
Role Overview
We are looking for a Senior CAD Engineer to deploy and support our front end tools, to develop scripts to automate regression and debug flows, to work along with our design, implementation and verification teams.
What you'll do
Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification.
Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD)
Streamline utilization of compute infrastructure using load distribution tools
Identify and prioritize needs of internal users and develop capabilities for them
Proficiently use scripts to integrate tools, repos and compute infrastructure
Configure and maintain project progress Dashboards.
Interface with EDA vendors for license and tool installations
Deploy tools and methodologies across geographies for global teams working together
What you need to have
B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics)
10+ years of relevant experience in CAD or allied disciplines
4+ years in a CAD role for a several 100 million gate Silicon ASIC project
Knowledge and understanding of ASIC flow
Proficiency in python, bash, c, Makefiles
Proficiency in administration of Linux systems (such as Redhat Enterprise)
Proficiency in distributed version control such as Git and/or Mercurial (Hg)
Eager to learn, fast pick up and timely execution
Experience in working with the standard CAD tools that are prevalent in the industry
Nice-to-haves
Experience with Kubernetes or LSF Systems
Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows
Experience with Javascript, CSS, and Web development frameworks
Work Location: Bangalore
Full-Time
Role Overview
We are looking for a Senior CAD Engineer to deploy and support our front end tools, to develop scripts to automate regression and debug flows, to work along with our design, implementation and verification teams.
What you'll do
Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification.
Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD)
Streamline utilization of compute infrastructure using load distribution tools
Identify and prioritize needs of internal users and develop capabilities for them
Proficiently use scripts to integrate tools, repos and compute infrastructure
Configure and maintain project progress Dashboards.
Interface with EDA vendors for license and tool installations
Deploy tools and methodologies across geographies for global teams working together
What you need to have
B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics)
10+ years of relevant experience in CAD or allied disciplines
4+ years in a CAD role for a several 100 million gate Silicon ASIC project
Knowledge and understanding of ASIC flow
Proficiency in python, bash, c, Makefiles
Proficiency in administration of Linux systems (such as Redhat Enterprise)
Proficiency in distributed version control such as Git and/or Mercurial (Hg)
Eager to learn, fast pick up and timely execution
Experience in working with the standard CAD tools that are prevalent in the industry
Nice-to-haves
Experience with Kubernetes or LSF Systems
Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows
Experience with Javascript, CSS, and Web development frameworks
Apply for this position
Application Status
Application Draft
In Progress
Submit Application
Pending
Review Process
Expected within 5-7 days
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